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authorDuncan Smith2010-11-09 23:48:43 -0800
committerDuncan Smith2010-11-09 23:48:43 -0800
commita3638a4d99bf53216c6c74d90b50c4d1429d64c4 (patch)
tree39f2bd87022de43a76080e7e198992a5a752a545 /opcodes_fd_cb.asm
parentefe2d323418042842d344e076dcac1da734785f3 (diff)
Added guards around all routines that touch ePC or eSP.
These guards have one major fault I can see. I put them as early in the routine as possible, but it's still a distinct possibility that the 68k interrupt will fire between move.b (epc)+,d0 in macro DONE of one instruction and the call to HOLD_INTS in the following instruction. I don't have a good solution to this. I can use the hardware interrupt holding support to make everything a critical section except for the cycle gap before that instruction, but that makes _every_ instruction 24 cycles slower. I don't consider that an acceptable solution.
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