diff options
| -rw-r--r-- | 680.inc | 4 | ||||
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | debug.c | 14 | ||||
| -rw-r--r-- | loader.c | 9 | ||||
| -rw-r--r-- | ports.asm | 20 |
5 files changed, 42 insertions, 7 deletions
@@ -11,11 +11,11 @@ ehl EQUR d6 eixy EQUR d7 SAVEREG MACRO - movem d3-d7/a3-a6,-(sp) + movem.l d3-d7/a3-a6,-(sp) ENDM RESTREG MACRO - movem (sp)+,d3-d7/a3-a6 + movem.l (sp)+,d3-d7/a3-a6 ENDM ;; pushm MACRO @@ -1,6 +1,6 @@ ASM_FILES=alu.asm flags.asm opcodes.asm ports.asm interrupts.asm main.asm ASM=main.asm -C_FILES=loader.c bankswap.c video.c misc.c +C_FILES=loader.c bankswap.c video.c misc.c debug.c TIGCCFLAGS=-Wall CFLAGS=-Wall -ltifiles @@ -0,0 +1,14 @@ +/* Debugging routines for 680 project. + * + * Includes debug output. + * + * Copyright 2010, Duncan Smith + * GPL + */ + +#include <stdio.h> + +void char_draw(char c) +{ + putchar((short)c); +} @@ -12,7 +12,12 @@ HANDLE page_handles[256]; -char infloop[16] = { 0xC3, 0x40, 0, 0, 0, 0 }; +char infloop[16] = { 0xC3, 0x40, // JP 4000h + 0, 0, 0, 0 }; +char writestr[16] = { 0x3E, 0x41, // LD A,'A' + 0xD3, 0x00, // OUT 00h,A + 0xC3, 0x40, 0x00 // JP 4000h +}; void init_load(void); void *deref_page(int); @@ -58,7 +63,7 @@ void init_load(void) mem_page_0 = pages[0]; mem_page_loc_0 = 0; // mem_page_1 = pages[0x1f]; - mem_page_1 = infloop; + mem_page_1 = writestr; mem_page_loc_1 = 0x1f; mem_page_2 = pages[0]; mem_page_loc_2 = 0; @@ -4,7 +4,10 @@ ;; Port is in d0, byte is in d1 ;; Destroys a0 port_in: - movea lut_ports_in(pc,d0),a0 + andi.w #$ff,d0 + add.w d0,d0 + add.w d0,d0 + movea.l lut_ports_in(pc,d0),a0 jmp (a0) rts @@ -267,7 +270,10 @@ lut_ports_in: dc.l port_in_ff port_out: - movea lut_ports_out(pc,d0.w),a0 + andi.w #$ff,d0 + add.w d0,d0 + add.w d0,d0 + movea.l lut_ports_out(pc,d0.w),a0 jmp (a0) rts @@ -531,6 +537,16 @@ lut_ports_out: port_in_00: port_out_00: + ;; Temporary test harness. Writing to this port writes a + ;; character to the screen. + SAVEREG + andi.w #$ff,d1 + move.w d1,-(sp) + jsr char_draw + addq #2,sp + RESTREG + rts + port_in_01: port_out_01: port_in_02: |
