diff options
| -rw-r--r-- | alu.asm | 2 | ||||
| -rw-r--r-- | flags.asm | 8 | ||||
| -rw-r--r-- | loader.c | 2 | ||||
| -rw-r--r-- | main.asm | 5 | ||||
| -rw-r--r-- | opcodes.asm.m4 | 16 | ||||
| -rw-r--r-- | opcodes.inc.m4 | 2 | ||||
| -rw-r--r-- | ports.asm | 2 |
7 files changed, 19 insertions, 18 deletions
@@ -81,6 +81,8 @@ alu_or: alu_cp: ;; Same as SUB but the macro that calls this doesn't save the ;; result. + + ;; SPEED can hardcode one of the arguments to always be the A register. move.b d0,f_tmp_src_b move.b d1,f_tmp_dst_b move.b #1,f_tmp_byte @@ -62,8 +62,8 @@ FNC_ok: andi.b #%00000001,d1 rts - ;; Normalize and return inverse of emulated Zero bit (loaded - ;; into host zero flag) + ;; Normalize and return **INVERSE** of emulated Zero bit + ;; (loaded into host's zero flag) ;; Destroys d1 f_norm_z: @@ -76,7 +76,7 @@ FNZ_ok: andi.b #%01000000,d1 rts - ;; Normalize and return inverse of emulated Parity/oVerflow + ;; Normalize and return **INVERSE** of emulated Parity/oVerflow ;; bit (loaded into host zero flag) ;; Destroys d1 @@ -192,7 +192,7 @@ flags_normalize: not.b d0 and.b d0,d1 ; Mask out all the unwanted bits not.b d0 - ori.b #%11000101,d0 + ori.b #%11000101,d0 ; These are the z80 flag register bits that can be derived from the 68k CCR. move.b d0,flag_valid-flag_storage(a3) or.b d1,flag_byte-flag_storage(a3) rts @@ -19,7 +19,7 @@ char writestr[16] = { 0x3E, 0x41, // LD A,'A' 0xC3, 0x40, 0x00 // JP 4000h }; -#include "testbenches/mine.testbench.h" +#include "testbenches/zexdoc.testbench.h" void init_load(void); void unload(void); @@ -40,12 +40,11 @@ xdef _ti89 ; xdef _ti92plus xdef __main - xdef _tigcc_native +; xdef _tigcc_native include "../tios.h" include "global.inc" - __main: movem.l d0-d7/a0-a6,-(sp) bsr init_load @@ -69,7 +68,7 @@ __main: include "alu.asm" emu_setup: - movea.l emu_plain_op,a5 + movea.l emu_op_00,a5 lea emu_run,a2 lea flag_storage,a3 move.w #$4000,d1 diff --git a/opcodes.asm.m4 b/opcodes.asm.m4 index 63ea0dc..31146c2 100644 --- a/opcodes.asm.m4 +++ b/opcodes.asm.m4 @@ -50,7 +50,7 @@ PUTW MACRO ; move.b d0,(a0) ENDM - ;; Push the word in \1 (register) using stack register a4. + ;; Push the word in \1 (register) using stack register esp. ;; Sadly, I can't trust the stack register to be aligned. ;; Destroys d2. @@ -60,11 +60,11 @@ PUTW MACRO ; PUSHW MACRO move.w \1,d2 LOHI d2 ;slow - move.b d2,-(a4) ; high byte - move.b \1,-(a4) ; low byte + move.b d2,-(esp) ; high byte + move.b \1,-(esp) ; low byte ENDM - ;; Pop the word at the top of stack a4 into \1. + ;; Pop the word at the top of stack esp into \1. ;; Destroys d0. ;; \1_h <- (SP+1) @@ -101,7 +101,7 @@ _align SET 0 START MACRO ORG emu_plain_op+_align _align SET _align+$40 ; opcode routine length - jmp do_interrupt ; for interrupt routines + bra.w do_interrupt ; for interrupt routines ENDM ;; LOHI/HILO are hideously slow for instructions used often. @@ -1710,6 +1710,7 @@ OPCODE(b7,« ;; COMPARE instruction + ;; Tests the argument against A F_CP_B MACRO ;; XXX deal with \2 or \1 being d1 or d0 move.b \2,d1 @@ -1797,7 +1798,7 @@ OPCODE(c1,« ; S10 T ;; PC <- immed.w OPCODE(c2,« bsr f_norm_z - bne.s emu_op_c3 + beq.s emu_op_c3 add.l #2,epc ») ;nok @@ -1809,7 +1810,6 @@ OPCODE(c3,« bsr deref movea.l a0,epc »,36,,12) - ;nok ;; CALL NZ,immed.w ;; If ~Z, CALL immed.w @@ -1871,7 +1871,7 @@ OPCODE(c9,« ;; If Z, jump OPCODE(ca,« bsr f_norm_z - beq emu_op_c3 + bne emu_op_c3 add.l #2,epc ») ;nok diff --git a/opcodes.inc.m4 b/opcodes.inc.m4 index fd225d4..b4c35b6 100644 --- a/opcodes.inc.m4 +++ b/opcodes.inc.m4 @@ -14,4 +14,4 @@ $2 undefine(«label»)dnl DONE»)dnl dnl -define(«INT_OFFSET», 6)dnl +define(«INT_OFFSET», 4)dnl @@ -271,11 +271,11 @@ lut_ports_in: port_out: andi.w #$ff,d0 + ;; This is the fastest way to shift left 2 bits. :S add.w d0,d0 add.w d0,d0 movea.l lut_ports_out(pc,d0.w),a0 jmp (a0) - rts lut_ports_out: dc.l port_out_00 |