diff options
| -rw-r--r-- | README.markdown | 10 | ||||
| -rw-r--r-- | instruction-timing.gnumeric | bin | 12406 -> 12410 bytes | |||
| -rw-r--r-- | opcodes.asm.m4 | 41 |
3 files changed, 29 insertions, 22 deletions
diff --git a/README.markdown b/README.markdown index 2c39862..7f1c6b5 100644 --- a/README.markdown +++ b/README.markdown @@ -44,7 +44,7 @@ instruction with a fixed 42 cycle overhead: (Using techniques borrowed from [Tezxas](http://tezxas.ticalc.org/technica.htm) I will be able to get -this to 30 cycles.) +this to 26 cycles.) From there, an instruction will take anywhere from 0 to, well, lots of additional cycles. Generally, however, it will take under 50, for 92 @@ -66,3 +66,11 @@ expected. * [More z80 instruction set reference](http://nemesis.lonestar.org/computers/tandy/software/apps/m4/qd/opcodes.html) * [Details on flags and other side effects](http://www.gaby.de/z80/z80code.htm) +Incompatibilities with Real Hardware +------------------------------------ + +1. PC-relative accesses (reads, writes, jumps) across page boundaries + may not work. This is apparently a rare enough occurence that + ignoring it is reasonable. + +2. diff --git a/instruction-timing.gnumeric b/instruction-timing.gnumeric Binary files differindex 0965839..58a6f30 100644 --- a/instruction-timing.gnumeric +++ b/instruction-timing.gnumeric diff --git a/opcodes.asm.m4 b/opcodes.asm.m4 index 051d33e..fe92245 100644 --- a/opcodes.asm.m4 +++ b/opcodes.asm.m4 @@ -344,18 +344,15 @@ OPCODE(0f,« ;; if B not zero ;; No flags ;; 24 bytes - ;; take: 22+4+ 8+8+4+300+8+94+4+22 = 474 - ;; skip: 22+4+10+ 22 = 58 + ;; take: 22+4+ 8+8+4+8+22 = 76 + ;; skip: 22+4+10+ 22 = 58 OPCODE(10,« LOHI ebc subq.b #1,ebc beq.s local(end) ; slooooow FETCHBI d1 - move.l epc,a0 - bsr underef - add.w d1,d0 ; ??? Can I avoid underef/deref cycle? - bsr deref - move.l a0,epc + ext.w d1 + add.w d1,epc local(end): HILO ebc »,,,32) @@ -430,14 +427,18 @@ OPCODE(17,« ;; PC <- immed.b ;; Branch relative by a signed immediate byte ;; No flags + ;; 20 cycles + + ;; XXX + ;; Yes, I can avoid the underef/deref cycle. To do so, put a + ;; sled of emulator trap instructions on either side of each + ;; 16k page. When that trap is executed, undo the shortcut + ;; and redo it by the book. + OPCODE(18,« clr.w d1 FETCHBI d1 - move.l epc,a0 - bsr underef - add.w d0,d1 ; ??? Can I avoid underef/deref cycle? - bsr deref - move.l a0,epc + add.w d1,epc ») ;nok @@ -505,8 +506,8 @@ OPCODE(1f,« ;; PC <- PC+immed.b ;; No flags ;; 10 bytes - ;; take: 40+10+422(=JR immed.b) = 472 - ;; skip: 40+12+12 = 64 + ;; take: 40+10+20(=JR immed.b) = 70 + ;; skip: 40+12+12 = 64 OPCODE(20,« bsr f_norm_z ;; if the emulated Z flag is set, this will be clear @@ -573,20 +574,20 @@ OPCODE(26,« ;; DAA ;; Decrement, adjust accum ;; http://www.z80.info/z80syntx.htm#DAA - ;; Flags: oh lord they're fucked up - ;; XXX DO THIS + ;; Flags: ummm, go find a manual. + ;; XXX ;; ? cycles OPCODE(27,« F_PAR eaf ») ;nok - ;; JR Z,immed.b + ;; JR Z,immed.b ;; If zero ;; PC <- PC+immed.b ;; SPEED can be made faster ;; No flags - ;; ~472 cycles + ;; ~130 cycles OPCODE(28,« bsr f_norm_z bne emu_op_18 @@ -747,9 +748,7 @@ OPCODE(38,« OPCODE(39,« move.l esp,a0 bsr underef - F_ADD_W ehl,d0 ; ??? Can I avoid underef/deref cycle? - bsr deref - move.l a0,esp + F_ADD_W d0,ehl ») ;nok |