From ddd3b3267a0c434561840080eb73493572aaffa0 Mon Sep 17 00:00:00 2001 From: Astrid Smith Date: Mon, 14 Jun 2010 20:26:49 -0700 Subject: Done with my first pass through the 1-byte opcodes. --- flags.asm | 12 + interrupts.asm | 4 + main.asm | 193 +++++++++-- ports.asm | 1035 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1220 insertions(+), 24 deletions(-) create mode 100644 interrupts.asm diff --git a/flags.asm b/flags.asm index aa04118..928a6e7 100644 --- a/flags.asm +++ b/flags.asm @@ -84,6 +84,18 @@ FNPV_ok: andi.b #%00000100,d1 rts + ;; Normalize and return Sign bit (loaded into Z bit). + ;; Destroys d1 +f_norm_sign: + move.b flag_valid-flag_storage(a3),d1 + andi.b #%01000000,d1 + bne.s FNsign_ok ; Bit is already valid + bsr flags_normalize +FNsign_ok: + move.b flag_byte-flag_storage(a3),d1 + andi.b #%01000000,d1 + rts + ;; Routine to turn 68k flags into z80 flags. ;; Preconditions: ;; Flags to change are noted in d0 by a 1 bit diff --git a/interrupts.asm b/interrupts.asm new file mode 100644 index 0000000..f76a0ff --- /dev/null +++ b/interrupts.asm @@ -0,0 +1,4 @@ +ints_stop: + rts +ints_start: + rts diff --git a/main.asm b/main.asm index 7a5d870..df9dc2c 100644 --- a/main.asm +++ b/main.asm @@ -46,15 +46,17 @@ ;; Macro to read a byte from main memory at register \1. Puts ;; the byte read in \2. -FETCHB MACRO ; 14 cycles, 4 bytes - ;; XXX deref - move.b 0(a6,\1.w),\2 +FETCHB MACRO + move.w \1,d1 + bsr deref + move.b (a0),\2 ENDM ;; Macro to write a byte in \1 to main memory at \2 (regs only) -PUTB MACRO ; 14 cycles, 4 bytes - ;; XXX deref - move.b \1,0(a6,\2) +PUTB MACRO + move.w \2,d1 + bsr deref + move.b \1,(a0) ENDM ;; Macro to read a word from main memory at register \1 @@ -79,6 +81,7 @@ PUTW MACRO ; 14 cycles, 4 bytes ENDM ;; Push the word in \1 (register) using stack register a4. + ;; Sadly, I can't trust the stack register to be aligned. ;; Destroys d0. ;; (SP-2) <- \1_l @@ -166,13 +169,6 @@ DONE MACRO ;; == Special Opcode Macros ======================================== - ;; Do an ADD \1,\2 -F_ADD_W MACRO - ENDM - ;; Do an SUB \1,\2 -F_SUB_W MACRO - ENDM - ;; INC and DEC macros F_INC_B MACRO ENDM @@ -206,6 +202,7 @@ _main: include "flags.asm" include "ports.asm" + include "interrupts.asm" emu_setup: movea emu_plain_op,a5 @@ -1868,7 +1865,8 @@ emu_op_c3: ; S12 T36 emu_op_c4: ;; CALL NZ,immed.w ;; If ~Z, CALL immed.w - ;; XXX do this + bsr f_norm_z + bne emu_op_cd DONE START @@ -1886,8 +1884,8 @@ emu_op_c6: START emu_op_c7: - ;; RST immed.b - ;; CALL 0 + ;; RST &0 + ;; == CALL 0 ;; XXX check ;; XXX FIX D2 move.l d2,d1 @@ -1930,7 +1928,8 @@ emu_op_cb: ; prefix START emu_op_cc: ;; CALL Z,immed.w - ;; XXX do this + bsr f_norm_z + beq emu_op_cd DONE START @@ -1993,7 +1992,8 @@ emu_op_d3: START emu_op_d4: ;; CALL NC,immed.w - ;; XXX do this + bsr f_norm_c + beq emu_op_cd DONE START @@ -2049,7 +2049,8 @@ emu_op_db: START emu_op_dc: ;; CALL C,immed.w - ;; XXX do this + bsr f_norm_c + bne emu_op_cd DONE START @@ -2086,24 +2087,71 @@ emu_op_e1: START emu_op_e2: - ;; EX (SP),HL - ;; Exchange + ;; JP PO,immed.w + bsr f_norm_pv + beq emu_op_c3 + DONE + START emu_op_e3: + ;; EX (SP),HL + ;; Exchange + POPW d1 + PUSHW d6 + move.w d1,d6 + DONE + START emu_op_e4: + ;; CALL PO,immed.w + ;; if parity odd (P=0), call + bsr f_norm_pv + beq emu_op_cd + DONE + START emu_op_e5: + ;; PUSH HL + PUSHW d6 + DONE + START emu_op_e6: + ;; AND immed.b + FETCHBI d1 + F_AND_B d1,d3 + DONE + START emu_op_e7: + ;; RST &20 + ;; == CALL 20 + ;; XXX do this + DONE + START emu_op_e8: + ;; RET PE + ;; If parity odd (P zero), return + bsr f_norm_pv + bne emu_op_c9 + DONE + START emu_op_e9: + ;; JP (HL) + FETCHB d6,d1 + bsr deref + movea a0,a6 + DONE + START emu_op_ea: + ;; JP PE,immed.w + bsr f_norm_pv + bne emu_op_c3 + DONE + START emu_op_eb: ;; EX DE,HL @@ -2112,51 +2160,148 @@ emu_op_eb: START emu_op_ec: + ;; CALL PE,immed.w + ;; If parity even (P=1), call + bsr f_norm_c + bne emu_op_cd + DONE + START emu_op_ed: ; prefix - movea.w emu_op_undo_ed(pc),a2 + DONE + START emu_op_ee: + ;; XOR immed.b + FETCHBI d1 + F_XOR_B d1,d3 + DONE + START emu_op_ef: + ;; RST &28 + ;; == CALL 28 + ;; XXX DO THIS + DONE + START emu_op_f0: + ;; RET P + ;; Return if Positive + bsr f_norm_sign + beq emu_op_c9 ; RET + DONE + START emu_op_f1: + ;; POP AF + ;; SPEED this can be made faster ... + POPW d3 + move.w d3,flag_byte-flag_storage(a3) + move.b #$ff,flag_valid-flag_storage(a3) + DONE + START emu_op_f2: + ;; JP P,immed.w + bsr f_norm_sign + beq emu_op_c3 ; JP + DONE + START emu_op_f3: + ;; DI + bsr ints_stop + START emu_op_f4: + ;; CALL P,&0000 + ;; Call if positive (S=0) + bsr f_norm_sign + beq emu_op_cd + DONE + START emu_op_f5: + ;; PUSH AF + bsr flags_normalize + LOHI d3 + move.b flag_byte-flag_storage(a3),d3 + HILO d3 + PUSHW d3 + DONE + START emu_op_f6: + ;; OR immed.b + FETCHBI d1 + F_OR_B d1,d3 + DONE + START emu_op_f7: + ;; RST &30 + ;; == CALL 30 + ;; XXX do this + DONE + START emu_op_f8: + ;; RET M + ;; Return if Sign == 1, minus + bsr f_norm_sign + bne emu_op_c9 ; RET + DONE + START emu_op_f9: + ;; LD SP,HL + ;; SP <- HL + move.w d6,d1 + bsr deref + movea a0,a4 + DONE + START emu_op_fa: + ;; JP M,immed.w + bsr f_norm_sign + bne emu_op_c3 ; JP + DONE + START -emu_op_fb:p +emu_op_fb: ;; EI + bsr ints_start + DONE START emu_op_fc: + ;; CALL M,immed.w + ;; Call if minus (S=1) + bsr f_norm_sign + bne emu_op_cd + DONE + START emu_op_fd: ; prefix ;; swap IY, HL - movea.w emu_op_undo_fd(pc),a2 + START emu_op_fe: + ;; CP immed.b + FETCHBI d1 + F_CP_B d1,d3 + DONE + START emu_op_ff: + ;; RST &38 + ;; == CALL 38 + ;; XXX do this + DONE emu_op_undo_cb: diff --git a/ports.asm b/ports.asm index 4ca60f7..8244c3d 100644 --- a/ports.asm +++ b/ports.asm @@ -2,8 +2,1043 @@ ;; bit that's unique to TI calculators. ;; Port is in d0, byte is in d1 + ;; Destroys a0 port_in: + movea lut_ports_in(pc,d0),a0 + jmp (a0) rts port_out: + ;; Fix this to work properly ... +; movea lut_ports_in(pc,d0),a0 + jmp (a0) rts + +lut_ports_in: + dc.l port_in_00 + dc.l port_in_01 + dc.l port_in_02 + dc.l port_in_03 + dc.l port_in_04 + dc.l port_in_05 + dc.l port_in_06 + dc.l port_in_07 + dc.l port_in_08 + dc.l port_in_09 + dc.l port_in_0a + dc.l port_in_0b + dc.l port_in_0c + dc.l port_in_0d + dc.l port_in_0e + dc.l port_in_0f + dc.l port_in_10 + dc.l port_in_11 + dc.l port_in_12 + dc.l port_in_13 + dc.l port_in_14 + dc.l port_in_15 + dc.l port_in_16 + dc.l port_in_17 + dc.l port_in_18 + dc.l port_in_19 + dc.l port_in_1a + dc.l port_in_1b + dc.l port_in_1c + dc.l port_in_1d + dc.l port_in_1e + dc.l port_in_1f + dc.l port_in_20 + dc.l port_in_21 + dc.l port_in_22 + dc.l port_in_23 + dc.l port_in_24 + dc.l port_in_25 + dc.l port_in_26 + dc.l port_in_27 + dc.l port_in_28 + dc.l port_in_29 + dc.l port_in_2a + dc.l port_in_2b + dc.l port_in_2c + dc.l port_in_2d + dc.l port_in_2e + dc.l port_in_2f + dc.l port_in_30 + dc.l port_in_31 + dc.l port_in_32 + dc.l port_in_33 + dc.l port_in_34 + dc.l port_in_35 + dc.l port_in_36 + dc.l port_in_37 + dc.l port_in_38 + dc.l port_in_39 + dc.l port_in_3a + dc.l port_in_3b + dc.l port_in_3c + dc.l port_in_3d + dc.l port_in_3e + dc.l port_in_3f + dc.l port_in_40 + dc.l port_in_41 + dc.l port_in_42 + dc.l port_in_43 + dc.l port_in_44 + dc.l port_in_45 + dc.l port_in_46 + dc.l port_in_47 + dc.l port_in_48 + dc.l port_in_49 + dc.l port_in_4a + dc.l port_in_4b + dc.l port_in_4c + dc.l port_in_4d + dc.l port_in_4e + dc.l port_in_4f + dc.l port_in_50 + dc.l port_in_51 + dc.l port_in_52 + dc.l port_in_53 + dc.l port_in_54 + dc.l port_in_55 + dc.l port_in_56 + dc.l port_in_57 + dc.l port_in_58 + dc.l port_in_59 + dc.l port_in_5a + dc.l port_in_5b + dc.l port_in_5c + dc.l port_in_5d + dc.l port_in_5e + dc.l port_in_5f + dc.l port_in_60 + dc.l port_in_61 + dc.l port_in_62 + dc.l port_in_63 + dc.l port_in_64 + dc.l port_in_65 + dc.l port_in_66 + dc.l port_in_67 + dc.l port_in_68 + dc.l port_in_69 + dc.l port_in_6a + dc.l port_in_6b + dc.l port_in_6c + dc.l port_in_6d + dc.l port_in_6e + dc.l port_in_6f + dc.l port_in_70 + dc.l port_in_71 + dc.l port_in_72 + dc.l port_in_73 + dc.l port_in_74 + dc.l port_in_75 + dc.l port_in_76 + dc.l port_in_77 + dc.l port_in_78 + dc.l port_in_79 + dc.l port_in_7a + dc.l port_in_7b + dc.l port_in_7c + dc.l port_in_7d + dc.l port_in_7e + dc.l port_in_7f + dc.l port_in_80 + dc.l port_in_81 + dc.l port_in_82 + dc.l port_in_83 + dc.l port_in_84 + dc.l port_in_85 + dc.l port_in_86 + dc.l port_in_87 + dc.l port_in_88 + dc.l port_in_89 + dc.l port_in_8a + dc.l port_in_8b + dc.l port_in_8c + dc.l port_in_8d + dc.l port_in_8e + dc.l port_in_8f + dc.l port_in_90 + dc.l port_in_91 + dc.l port_in_92 + dc.l port_in_93 + dc.l port_in_94 + dc.l port_in_95 + dc.l port_in_96 + dc.l port_in_97 + dc.l port_in_98 + dc.l port_in_99 + dc.l port_in_9a + dc.l port_in_9b + dc.l port_in_9c + dc.l port_in_9d + dc.l port_in_9e + dc.l port_in_9f + dc.l port_in_a0 + dc.l port_in_a1 + dc.l port_in_a2 + dc.l port_in_a3 + dc.l port_in_a4 + dc.l port_in_a5 + dc.l port_in_a6 + dc.l port_in_a7 + dc.l port_in_a8 + dc.l port_in_a9 + dc.l port_in_aa + dc.l port_in_ab + dc.l port_in_ac + dc.l port_in_ad + dc.l port_in_ae + dc.l port_in_af + dc.l port_in_b0 + dc.l port_in_b1 + dc.l port_in_b2 + dc.l port_in_b3 + dc.l port_in_b4 + dc.l port_in_b5 + dc.l port_in_b6 + dc.l port_in_b7 + dc.l port_in_b8 + dc.l port_in_b9 + dc.l port_in_ba + dc.l port_in_bb + dc.l port_in_bc + dc.l port_in_bd + dc.l port_in_be + dc.l port_in_bf + dc.l port_in_c0 + dc.l port_in_c1 + dc.l port_in_c2 + dc.l port_in_c3 + dc.l port_in_c4 + dc.l port_in_c5 + dc.l port_in_c6 + dc.l port_in_c7 + dc.l port_in_c8 + dc.l port_in_c9 + dc.l port_in_ca + dc.l port_in_cb + dc.l port_in_cc + dc.l port_in_cd + dc.l port_in_ce + dc.l port_in_cf + dc.l port_in_d0 + dc.l port_in_d1 + dc.l port_in_d2 + dc.l port_in_d3 + dc.l port_in_d4 + dc.l port_in_d5 + dc.l port_in_d6 + dc.l port_in_d7 + dc.l port_in_d8 + dc.l port_in_d9 + dc.l port_in_da + dc.l port_in_db + dc.l port_in_dc + dc.l port_in_dd + dc.l port_in_de + dc.l port_in_df + dc.l port_in_e0 + dc.l port_in_e1 + dc.l port_in_e2 + dc.l port_in_e3 + dc.l port_in_e4 + dc.l port_in_e5 + dc.l port_in_e6 + dc.l port_in_e7 + dc.l port_in_e8 + dc.l port_in_e9 + dc.l port_in_ea + dc.l port_in_eb + dc.l port_in_ec + dc.l port_in_ed + dc.l port_in_ee + dc.l port_in_ef + dc.l port_in_f0 + dc.l port_in_f1 + dc.l port_in_f2 + dc.l port_in_f3 + dc.l port_in_f4 + dc.l port_in_f5 + dc.l port_in_f6 + dc.l port_in_f7 + dc.l port_in_f8 + dc.l port_in_f9 + dc.l port_in_fa + dc.l port_in_fb + dc.l port_in_fc + dc.l port_in_fd + dc.l port_in_fe + dc.l port_in_ff + +lut_ports_out: + dc.l port_out_00 + dc.l port_out_01 + dc.l port_out_02 + dc.l port_out_03 + dc.l port_out_04 + dc.l port_out_05 + dc.l port_out_06 + dc.l port_out_07 + dc.l port_out_08 + dc.l port_out_09 + dc.l port_out_0a + dc.l port_out_0b + dc.l port_out_0c + dc.l port_out_0d + dc.l port_out_0e + dc.l port_out_0f + dc.l port_out_10 + dc.l port_out_11 + dc.l port_out_12 + dc.l port_out_13 + dc.l port_out_14 + dc.l port_out_15 + dc.l port_out_16 + dc.l port_out_17 + dc.l port_out_18 + dc.l port_out_19 + dc.l port_out_1a + dc.l port_out_1b + dc.l port_out_1c + dc.l port_out_1d + dc.l port_out_1e + dc.l port_out_1f + dc.l port_out_20 + dc.l port_out_21 + dc.l port_out_22 + dc.l port_out_23 + dc.l port_out_24 + dc.l port_out_25 + dc.l port_out_26 + dc.l port_out_27 + dc.l port_out_28 + dc.l port_out_29 + dc.l port_out_2a + dc.l port_out_2b + dc.l port_out_2c + dc.l port_out_2d + dc.l port_out_2e + dc.l port_out_2f + dc.l port_out_30 + dc.l port_out_31 + dc.l port_out_32 + dc.l port_out_33 + dc.l port_out_34 + dc.l port_out_35 + dc.l port_out_36 + dc.l port_out_37 + dc.l port_out_38 + dc.l port_out_39 + dc.l port_out_3a + dc.l port_out_3b + dc.l port_out_3c + dc.l port_out_3d + dc.l port_out_3e + dc.l port_out_3f + dc.l port_out_40 + dc.l port_out_41 + dc.l port_out_42 + dc.l port_out_43 + dc.l port_out_44 + dc.l port_out_45 + dc.l port_out_46 + dc.l port_out_47 + dc.l port_out_48 + dc.l port_out_49 + dc.l port_out_4a + dc.l port_out_4b + dc.l port_out_4c + dc.l port_out_4d + dc.l port_out_4e + dc.l port_out_4f + dc.l port_out_50 + dc.l port_out_51 + dc.l port_out_52 + dc.l port_out_53 + dc.l port_out_54 + dc.l port_out_55 + dc.l port_out_56 + dc.l port_out_57 + dc.l port_out_58 + dc.l port_out_59 + dc.l port_out_5a + dc.l port_out_5b + dc.l port_out_5c + dc.l port_out_5d + dc.l port_out_5e + dc.l port_out_5f + dc.l port_out_60 + dc.l port_out_61 + dc.l port_out_62 + dc.l port_out_63 + dc.l port_out_64 + dc.l port_out_65 + dc.l port_out_66 + dc.l port_out_67 + dc.l port_out_68 + dc.l port_out_69 + dc.l port_out_6a + dc.l port_out_6b + dc.l port_out_6c + dc.l port_out_6d + dc.l port_out_6e + dc.l port_out_6f + dc.l port_out_70 + dc.l port_out_71 + dc.l port_out_72 + dc.l port_out_73 + dc.l port_out_74 + dc.l port_out_75 + dc.l port_out_76 + dc.l port_out_77 + dc.l port_out_78 + dc.l port_out_79 + dc.l port_out_7a + dc.l port_out_7b + dc.l port_out_7c + dc.l port_out_7d + dc.l port_out_7e + dc.l port_out_7f + dc.l port_out_80 + dc.l port_out_81 + dc.l port_out_82 + dc.l port_out_83 + dc.l port_out_84 + dc.l port_out_85 + dc.l port_out_86 + dc.l port_out_87 + dc.l port_out_88 + dc.l port_out_89 + dc.l port_out_8a + dc.l port_out_8b + dc.l port_out_8c + dc.l port_out_8d + dc.l port_out_8e + dc.l port_out_8f + dc.l port_out_90 + dc.l port_out_91 + dc.l port_out_92 + dc.l port_out_93 + dc.l port_out_94 + dc.l port_out_95 + dc.l port_out_96 + dc.l port_out_97 + dc.l port_out_98 + dc.l port_out_99 + dc.l port_out_9a + dc.l port_out_9b + dc.l port_out_9c + dc.l port_out_9d + dc.l port_out_9e + dc.l port_out_9f + dc.l port_out_a0 + dc.l port_out_a1 + dc.l port_out_a2 + dc.l port_out_a3 + dc.l port_out_a4 + dc.l port_out_a5 + dc.l port_out_a6 + dc.l port_out_a7 + dc.l port_out_a8 + dc.l port_out_a9 + dc.l port_out_aa + dc.l port_out_ab + dc.l port_out_ac + dc.l port_out_ad + dc.l port_out_ae + dc.l port_out_af + dc.l port_out_b0 + dc.l port_out_b1 + dc.l port_out_b2 + dc.l port_out_b3 + dc.l port_out_b4 + dc.l port_out_b5 + dc.l port_out_b6 + dc.l port_out_b7 + dc.l port_out_b8 + dc.l port_out_b9 + dc.l port_out_ba + dc.l port_out_bb + dc.l port_out_bc + dc.l port_out_bd + dc.l port_out_be + dc.l port_out_bf + dc.l port_out_c0 + dc.l port_out_c1 + dc.l port_out_c2 + dc.l port_out_c3 + dc.l port_out_c4 + dc.l port_out_c5 + dc.l port_out_c6 + dc.l port_out_c7 + dc.l port_out_c8 + dc.l port_out_c9 + dc.l port_out_ca + dc.l port_out_cb + dc.l port_out_cc + dc.l port_out_cd + dc.l port_out_ce + dc.l port_out_cf + dc.l port_out_d0 + dc.l port_out_d1 + dc.l port_out_d2 + dc.l port_out_d3 + dc.l port_out_d4 + dc.l port_out_d5 + dc.l port_out_d6 + dc.l port_out_d7 + dc.l port_out_d8 + dc.l port_out_d9 + dc.l port_out_da + dc.l port_out_db + dc.l port_out_dc + dc.l port_out_dd + dc.l port_out_de + dc.l port_out_df + dc.l port_out_e0 + dc.l port_out_e1 + dc.l port_out_e2 + dc.l port_out_e3 + dc.l port_out_e4 + dc.l port_out_e5 + dc.l port_out_e6 + dc.l port_out_e7 + dc.l port_out_e8 + dc.l port_out_e9 + dc.l port_out_ea + dc.l port_out_eb + dc.l port_out_ec + dc.l port_out_ed + dc.l port_out_ee + dc.l port_out_ef + dc.l port_out_f0 + dc.l port_out_f1 + dc.l port_out_f2 + dc.l port_out_f3 + dc.l port_out_f4 + dc.l port_out_f5 + dc.l port_out_f6 + dc.l port_out_f7 + dc.l port_out_f8 + dc.l port_out_f9 + dc.l port_out_fa + dc.l port_out_fb + dc.l port_out_fc + dc.l port_out_fd + dc.l port_out_fe + dc.l port_out_ff + +port_in_00: +port_out_00: +port_in_01: +port_out_01: +port_in_02: +port_out_02: +port_in_03: +port_out_03: +port_in_04: +port_out_04: +port_in_05: +port_out_05: +port_in_06: +port_out_06: +port_in_07: +port_out_07: +port_in_08: +port_out_08: +port_in_09: +port_out_09: +port_in_0a: +port_out_0a: +port_in_0b: +port_out_0b: +port_in_0c: +port_out_0c: +port_in_0d: +port_out_0d: +port_in_0e: +port_out_0e: +port_in_0f: +port_out_0f: +port_in_10: +port_out_10: +port_in_11: +port_out_11: +port_in_12: +port_out_12: +port_in_13: +port_out_13: +port_in_14: +port_out_14: +port_in_15: +port_out_15: +port_in_16: +port_out_16: +port_in_17: +port_out_17: +port_in_18: +port_out_18: +port_in_19: +port_out_19: +port_in_1a: +port_out_1a: +port_in_1b: +port_out_1b: +port_in_1c: +port_out_1c: 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+port_in_fb: +port_out_fb: +port_in_fc: +port_out_fc: +port_in_fd: +port_out_fd: +port_in_fe: +port_out_fe: +port_in_ff: +port_out_ff: -- cgit v1.2.3 From c66aae0e07d9bccd69f58cc8c492ff2eaa2f2f74 Mon Sep 17 00:00:00 2001 From: Astrid Smith Date: Mon, 14 Jun 2010 22:37:58 -0700 Subject: Removed LABEL-flag_storage(a3) business, as A68k was choking on it :( --- flags.asm | 20 +++--- main.asm | 242 ++++++++++++++++++++++++++++++++++++++++---------------------- 2 files changed, 166 insertions(+), 96 deletions(-) diff --git a/flags.asm b/flags.asm index 928a6e7..a7c6c4b 100644 --- a/flags.asm +++ b/flags.asm @@ -17,15 +17,16 @@ F_CLEAR MACRO ;; Sets or clears the bit explicitly. ;; ;; Byte for which parity is calculated must be in \1. High - ;; byte of \1.w must be zero, using d0 is suggested. (d1 + ;; byte of \1.w must be zero, using d0 is suggested. (a0,d1 ;; destroyed) F_PAR MACRO - ori.b #%00000100,flag_valid-flag_storage(a3) ; ??/4 - move.b flag_byte-flag_storage(a3),d1 ; ??/2 - andi.b #%11111011,d1 ; ??/4 - or.b lut_parity-flag_storage(a3,\1.w),d1 ; ??/4 - move.b d1,flag_byte-flag_storage(a3) ; ??/2 + ori.b #%00000100,(flag_valid).w ; ??/4 + move.b (flag_byte).w,d1 ; ??/2 + andi.b #%11111011,d1 ; ??/4 + lea (lut_parity).w,a0 + or.b 0(a0,\1.w),d1 ; ??/4 + move.b d1,(flag_byte).w ; ??/2 ENDM ;xxx cycles (!) @@ -37,9 +38,9 @@ F_OVFL MACRO ;; Save the two operands from ADD \1,\2 F_ADD_SAVE MACRO - move.b \1,f_tmp_src_b-flag_storage(a3) - move.b \2,f_tmp_dst_b-flag_storage(a3) - move.b #$01,f_tmp_byte-flag_storage(a3) + move.b \1,(f_tmp_src_b).w + move.b \2,(f_tmp_dst_b).w + move.b #$01,(f_tmp_byte).w F_SET #% ENDM @@ -131,6 +132,7 @@ f_host_sr: ds.b 0 f_host_ccr: ds.b 0 EVEN + ;; DO NOT REARRANGE THESE. flag_byte: ds.b 0 ; Byte of all flags flag_valid: ds.b 0 ; Validity mask -- 1 if valid. diff --git a/main.asm b/main.asm index df9dc2c..2e8152b 100644 --- a/main.asm +++ b/main.asm @@ -14,7 +14,7 @@ ;;; A6 = emulated PC XXX ;;; A5 = instruction table base pointer ;;; A4 = emulated SP XXX -;;; A3 = constants address (see flags.asm) +;;; A3 = ;;; A2 = ;;; A1 = ;;; A0 = @@ -168,6 +168,12 @@ DONE MACRO ;; == Special Opcode Macros ======================================== + ;; Do an ADD \1,\2 +F_ADD_W MACRO + ENDM + ;; Do an SUB \1,\2 +F_SUB_W MACRO + ENDM ;; INC and DEC macros F_INC_B MACRO @@ -177,9 +183,11 @@ F_DEC_B MACRO ENDM F_INC_W MACRO + addq.w #1,\1 ENDM F_DEC_W MACRO + subq.w #1,\1 ENDM ;; I might be able to unify rotation flags or maybe use a @@ -207,7 +215,6 @@ _main: emu_setup: movea emu_plain_op,a5 lea emu_fetch(pc),a2 - lea flag_storage(pc),a3 ; Thanks to Lionel ;; XXX finish rts @@ -215,30 +222,48 @@ emu_setup: ;; Take a virtual address in d1 and dereference it. Returns the ;; host address in a0. Destroys a0, d0. -;; XXX I added a masking of the upper bits of the Z80 address (d1) before translating them to host address. -;; Please double-check, but AFAICT, it's the right thing to do. - - ;; XXX these use the old setup, replace this with a writable - ;; LUT. deref: move.w d1,d0 andi.w #$3FFF,d0 movea.w d0,a0 move.w d1,d0 - andi.w #$C000,d0 - rol.w #5,d0 - jmp 0(pc,d0.w) - ;; 00 - adda.l a1,a0 - rts - ;; 01 - adda.l a2,a0 + andi.w #$C000,d0 ; Can cut this out by pre-masking the table. + rol.w #2,d0 + adda.l deref_table(pc,d0),a0 rts - ;; 02 - adda.l a3,a0 - rts - ;; 03 - adda.l a4,a0 + +deref_table: +ref_0: dc.l 0 ; bank 0 +ref_1: dc.l 0 ; bank 1 +ref_2: dc.l 0 ; bank 2 +ref_3: dc.l 0 ; bank 3 + + ;; Take a physical address in a0 and turn it into a virtual + ;; address in d0 + ;; Destroys +underef: + move.l a0,d0 + sub.l ref_0(pc,d0),d0 + bmi underef_not0 + cmpi.l #$10000,d0 + bmi underef_thatsit +underef_not0: + move.l a0,d0 + sub.l ref_1(pc,d0),d0 + bmi underef_not1 + cmpi.l #$10000,d0 + bmi underef_thatsit +underef_not1: + move.l a0,d0 + sub.l ref_2(pc,d0),d0 + bmi underef_not2 + cmpi.l #$10000,d0 + bmi underef_thatsit +underef_not2: + move.l a0,d0 + sub.l ref_3(pc,d0),d0 + ;; if that fails too, well shit man! +underef_thatsit: rts @@ -305,25 +330,25 @@ emu_op_03: ; S2 T4 ;; INC BC ;; BC <- BC+1 ;; No flags - addq.w #1,d4 + F_INC_W d4 DONE START emu_op_04: ;; INC B ;; B <- B+1 - ;; XXX FLAGS - add.w #$0100,d4 ; 8 - DONE ; 8 - ;16 cycles + LOHI d4 + F_INC_B d4 + HILO d4 + DONE START emu_op_05: ;; DEC B ;; B <- B-1 - ;; Flags: S,Z,H changed, P=oVerflow, N set, C left - ;; XXX FLAGS - sub.w #$0100,d4 + LOHI d4 + F_DEC_B d4 + HILO d4 DONE START @@ -341,6 +366,7 @@ emu_op_07: ; S2 T4 ;; RLCA ;; Rotate A left, carry bit gets top bit ;; Flags: H,N=0; C aff. + ;; XXX flags rol.b #1,d3 DONE @@ -356,8 +382,7 @@ emu_op_09: ;; ADD HL,BC ;; HL <- HL+BC ;; Flags: H, C aff.; N=0 - ;; XXX FLAGS - add.w d4,d6 + F_ADD_W d4,d6 DONE START @@ -373,7 +398,7 @@ emu_op_0b: ; S2 T4 ;; DEC BC ;; BC <- BC-1 ;; No flags - subq.w #1,d4 + F_DEC_W d4 DONE START @@ -381,8 +406,7 @@ emu_op_0c: ;; INC C ;; C <- C+1 ;; Flags: S,Z,H aff.; P=overflow, N=0 - ;; XXX FLAGS - addq.b #1,d4 + F_INC_B d4 DONE START @@ -390,8 +414,7 @@ emu_op_0d: ;; DEC C ;; C <- C-1 ;; Flags: S,Z,H aff., P=overflow, N=1 - ;; XXX FLAGS - subq.b #1,d4 + F_DEC_B d4 DONE START @@ -411,7 +434,7 @@ emu_op_0f: DONE START -emu_op_10: ; S14 T?? +emu_op_10: ; S32 ;; DJNZ immed.w ;; Decrement B ;; and branch by immed.b @@ -421,7 +444,11 @@ emu_op_10: ; S14 T?? subq.b #1,d4 beq end_10 ; slooooow FETCHBI d1 - add.w d1,a6 ; XXX deref? + move a6,a0 + bsr underef + add.w d1,d0 ; ??? Can I avoid underef/deref cycle? + bsr deref + move a0,a6 end_10: HILO d4 DONE @@ -444,7 +471,7 @@ emu_op_12: emu_op_13: ;; INC DE ;; No flags - addq.w #1,d5 + F_INC_W d5 DONE START @@ -452,7 +479,7 @@ emu_op_14: ;; INC D ;; Flags: S,Z,H aff.; P=overflow, N=0 LOHI d5 - addq.b #1,d5 + F_INC_B d5 HILO d5 DONE @@ -461,7 +488,7 @@ emu_op_15: ;; DEC D ;; Flags: S,Z,H aff.; P=overflow, N=1 LOHI d5 - subq.b #1,d5 + F_DEC_B d5 HILO d5 DONE @@ -478,6 +505,7 @@ emu_op_16: emu_op_17: ;; RLA ;; Flags: P,N=0; C aff. + ;; XXX flags roxl.b #1,d3 DONE @@ -487,7 +515,11 @@ emu_op_18: ;; Branch relative by a signed immediate byte ;; No flags FETCHBI d1 - add.w d1,a6 ; XXX deref? + move a6,a0 + bsr underef + add.w d1,d0 ; ??? Can I avoid underef/deref cycle? + bsr deref + move a0,a6 DONE START @@ -495,7 +527,7 @@ emu_op_19: ;; ADD HL,DE ;; HL <- HL+DE ;; Flags: H,C aff,; N=0 - add.w d5,d6 + F_ADD_W d5,d6 DONE START @@ -517,14 +549,14 @@ emu_op_1b: emu_op_1c: ;; INC E ;; Flags: S,Z,H aff.; P=overflow; N=0 - addq.b #1,d5 + F_INC_B d5 DONE START emu_op_1d: ;; DEC E ;; Flags: S,Z,H aff.; P=overflow, N=1 - subq.b #1,d5 + F_DEC_B d5 DONE START @@ -538,6 +570,7 @@ emu_op_1e: emu_op_1f: ;; RRA ;; Flags: H,N=0; C aff. + ;; XXX FLAGS roxr.b #1,d3 DONE @@ -582,7 +615,7 @@ emu_op_24: ;; INC H ;; Flags: S,Z,H aff.; P=overflow, N=0 LOHI d6 - addq.b #1,d6 + F_INC_B d6 HILO d6 DONE @@ -591,7 +624,7 @@ emu_op_25: ;; DEC H ;; Flags: S,Z,H aff.; P=overflow, N=1 LOHI d6 - subq.b #1,d6 + F_DEC_B d6 HILO d6 DONE @@ -622,6 +655,7 @@ emu_op_28: ;; PC <- PC+immed.b ;; SPEED can be made faster ;; No flags + bsr f_norm_z beq end_28 FETCHBI d1 add.w d1,a6 ; XXX deref? @@ -632,7 +666,7 @@ end_28: emu_op_29: ;; ADD HL,HL ;; Flags: - add.w d6,d6 + F_ADD_W d6,d6 DONE START @@ -646,19 +680,19 @@ emu_op_2a: START emu_op_2b: ;; DEC HL - subq.w #1,d6 + F_DEC_W d6 DONE START emu_op_2c: ;; INC L - addq.b #1,d6 + F_INC_B d6 DONE START emu_op_2d: ;; DEC L - subq.b #1,d6 + F_DEC_B d6 DONE START @@ -671,6 +705,7 @@ emu_op_2e: emu_op_2f: ;; CPL ;; A <- NOT A + ;; XXX flags not.b d3 DONE @@ -682,7 +717,11 @@ emu_op_30: bsr f_norm_c bne end_30 ; branch taken: carry set FETCHBI d1 - add.w d1,a6 ; XXX deref? + move a6,a0 + bsr underef + add.w d1,d0 ; ??? Can I avoid underef/deref cycle? + bsr deref + move a0,a6 end_30: DONE @@ -705,6 +744,7 @@ emu_op_32: START emu_op_33: ;; INC SP + ;; No flags ;; FYI: Do not have to deref because this will never cross a ;; page boundary. addq.w #1,a4 @@ -716,7 +756,7 @@ emu_op_34: ;; Increment byte ;; SPEED can be made faster FETCHB d6,d1 - addq.b #1,d1 + F_INC_B d1 PUTB d1,d6 DONE @@ -726,7 +766,7 @@ emu_op_35: ;; Decrement byte ;; SPEED can be made faster FETCHB d6,d1 - subq.b #1,d1 + F_DEC_B d1 PUTB d1,d6 DONE @@ -741,7 +781,11 @@ emu_op_36: emu_op_37: ;; SCF ;; Set Carry Flag - ;; XXX DO THIS + move.b #%00111011,(flag_valid).w + move.b d3,d1 + ori.b #%00000001,d1 + andi.b #%00101001,d1 + or.b d1,(flag_byte).w DONE START @@ -749,7 +793,8 @@ emu_op_38: ;; JR C,immed.b ;; If carry set ;; PC <- PC+immed.b - bcc end_38 + bsr f_norm_c + beq end_38 FETCHBI d1 add.w d1,a6 ; XXX deref? end_38: @@ -759,9 +804,11 @@ end_38: emu_op_39: ;; ADD HL,SP ;; HL <- HL+SP - swap d2 - add.w d6,d2 ; XXX fix this shit up - swap d2 + move a4,a0 + bsr underef + F_ADD_W d6,d0 ; ??? Can I avoid underef/deref cycle? + bsr deref + move a0,a4 DONE START @@ -774,19 +821,20 @@ emu_op_3a: START emu_op_3b: ;; DEC SP - subq.w #1,a4 + ;; No flags + subq.l #1,a4 DONE START emu_op_3c: ;; INC A - addq.b #1,d3 + F_INC_B d3 DONE START emu_op_3d: ;; DEC A - subq.b #1,d3 + F_DEC_B d3 DONE START @@ -799,7 +847,9 @@ emu_op_3e: emu_op_3f: ;; CCF ;; Toggle carry flag - ;; XXX DO THIS + bsr flags_normalize + ;; SZ5H3PNC + eor.b #%00010001,(flag_byte).w DONE START @@ -825,23 +875,22 @@ emu_op_41: emu_op_42: ;; LD B,D ;; B <- D - LOHI d4 ; 4 - LOHI d5 ; 4 - move.b d5,d4 ; 4 - HILO d4 ; 4 - HILO d5 ; 4 + ;; SPEED + LOHI d4 + LOHI d5 + move.b d5,d4 + HILO d4 + HILO d5 DONE - ;20 cycles START emu_op_43: ;; LD B,E ;; B <- E - LOHI d4 ; 4 + LOHI d4 move.b d4,d5 ; 4 - HILO d4 ; 4 + HILO d4 DONE - ; 12 cycles START emu_op_44: @@ -1299,10 +1348,10 @@ emu_op_7f: F_ADD_B MACRO ; 14 bytes? move.b \1,f_tmp_src_b ; preserve operands for flag work move.b \2,f_tmp_dst_b - move.b #0,flag_n - move.b #1,f_tmp_byte + move.b #1,(f_tmp_byte).w add \1,\2 - move sr,f_host_ccr + move sr,(f_host_ccr).w + move.w #0202,(flag_byte).w ENDM START @@ -1364,8 +1413,17 @@ emu_op_87: ;; Do an ADC \2,\1 -F_ADC_B MACRO - ;; XXX +F_ADC_B MACRO ; S34 + ;; XXX TOO BIG + bsr flags_normalize + move.b (flag_byte).w,d0 + andi.b #1,d0 + add.b \1,d0 + move.b d0,(f_tmp_src_b).w + move.b \2,(f_tmp_dst_b).w + add.b d0,\2 + move sr,(f_host_ccr).w + move.w #$0202,(flag_byte).w ENDM START @@ -1436,14 +1494,15 @@ emu_op_8f: ;; Do a SUB \2,\1 ;; XXX CHECK -F_SUB_B MACRO ;14 bytes? +F_SUB_B MACRO ;22 bytes? ;; XXX use lea and then d(an) if you have a spare register. - move.b \1,f_tmp_src_b ; preserve operands for flagging - move.b \2,f_tmp_dst_b - move.b #1,flag_n - move.b #1,f_tmp_byte + move.b \1,(f_tmp_src_b).w ; preserve operands for flagging + move.b \2,(f_tmp_dst_b).w + move.b #1,(f_tmp_byte).w + andi.b #%00000010,(flag_valid).w + move.b #%00000010,(flag_byte).w sub \1,\2 - move sr,f_host_ccr + move sr,(f_host_ccr).w ENDM START @@ -1451,7 +1510,6 @@ emu_op_90: ;; SUB A,B LOHI d4 F_SUB_B d4,d3 - add.b d4,d3 HILO d4 DONE @@ -1507,7 +1565,17 @@ emu_op_97: ;; Do a SBC \2,\1 F_SBC_B MACRO - ;; XXX + ;; XXX TOO BIG + bsr flags_normalize + move.b (flag_byte).w,d0 + andi.b #1,d0 + add.b \1,d0 + move.b d0,(f_tmp_src_b).w + move.b \2,(f_tmp_dst_b).w + sub.b d0,\2 + move sr,(f_host_ccr).w + move.w #$0202,(flag_byte).w + ENDM START @@ -2198,8 +2266,8 @@ emu_op_f1: ;; POP AF ;; SPEED this can be made faster ... POPW d3 - move.w d3,flag_byte-flag_storage(a3) - move.b #$ff,flag_valid-flag_storage(a3) + move.w d3,(flag_byte).w + move.b #$ff,(flag_valid).w DONE START @@ -2227,7 +2295,7 @@ emu_op_f5: ;; PUSH AF bsr flags_normalize LOHI d3 - move.b flag_byte-flag_storage(a3),d3 + move.b (flag_byte).w,d3 HILO d3 PUSHW d3 DONE -- cgit v1.2.3 From 55e34cb5c5e7ccbd150da9bde886a6f8ca5786b0 Mon Sep 17 00:00:00 2001 From: Astrid Smith Date: Mon, 14 Jun 2010 22:59:36 -0700 Subject: Fixed stupid constant error in underef --- alu.asm | 4 ++++ main.asm | 15 +++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) create mode 100644 alu.asm diff --git a/alu.asm b/alu.asm new file mode 100644 index 0000000..cce4011 --- /dev/null +++ b/alu.asm @@ -0,0 +1,4 @@ + ;; Parting out the big math/logic routines from the + ;; instruction dispatch table. + + diff --git a/main.asm b/main.asm index 2e8152b..1ecdc88 100644 --- a/main.asm +++ b/main.asm @@ -219,6 +219,13 @@ emu_setup: rts +;; |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| +;; _ __ ___ ___ _ __ ___ ___ _ __ _ _ ||||||||||||||||||||||||||| +;; | '_ ` _ \ / _ \ '_ ` _ \ / _ \| '__| | | | \\\\\\\\\\\\\\\\\\\\\\\\\\\ +;; | | | | | | __/ | | | | | (_) | | | |_| | ||||||||||||||||||||||||||| +;; |_| |_| |_|\___|_| |_| |_|\___/|_| \__, | /////////////////////////// +;; of the virtual type |___/ ||||||||||||||||||||||||||| +;; =============================================JJJJJJJJJJJJJJJJJJJJJJJJJJJ ;; Take a virtual address in d1 and dereference it. Returns the ;; host address in a0. Destroys a0, d0. @@ -240,24 +247,24 @@ ref_3: dc.l 0 ; bank 3 ;; Take a physical address in a0 and turn it into a virtual ;; address in d0 - ;; Destroys + ;; Destroys d0 underef: move.l a0,d0 sub.l ref_0(pc,d0),d0 bmi underef_not0 - cmpi.l #$10000,d0 + cmpi.l #$4000,d0 bmi underef_thatsit underef_not0: move.l a0,d0 sub.l ref_1(pc,d0),d0 bmi underef_not1 - cmpi.l #$10000,d0 + cmpi.l #$4000,d0 bmi underef_thatsit underef_not1: move.l a0,d0 sub.l ref_2(pc,d0),d0 bmi underef_not2 - cmpi.l #$10000,d0 + cmpi.l #$4000,d0 bmi underef_thatsit underef_not2: move.l a0,d0 -- cgit v1.2.3