From 230532164770650c105199a6da7bb178d3627b35 Mon Sep 17 00:00:00 2001
From: Duncan Smith
Date: Mon, 27 Dec 2010 22:36:40 -0800
Subject: Cleaned up interrupt routine, now it works properly.

Perhaps this is slower than necessary, particularly when interrupts
are disabled.
---
 interrupts.asm.m4 | 6 ++----
 main.asm          | 2 ++
 opcodes.asm.m4    | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/interrupts.asm.m4 b/interrupts.asm.m4
index cf2b195..404f02f 100644
--- a/interrupts.asm.m4
+++ b/interrupts.asm.m4
@@ -42,8 +42,8 @@ int_handler:
 int_nevermind:
 	rts
 do_interrupt:
-	;; todo: make this file m4'd
 	add.l	#INT_OFFSET,a5		; clear the interrupt flag
+	pea	0(a5,d0.w)		; allows us to rts properly
 
 	tst.b	int_enabled		; 4 cycles
 	beq.b	int_nevermind		; 8 cycles not taken
@@ -52,8 +52,6 @@ do_interrupt:
 	;; Since this is an instruction all its own, we have D0, D1,
 	;; and D2 available.
 
-	pop.l	a0
-
 	;; Interrupts are most often in mode 1, then mode 2, and
 	;; almost never in mode 0.
 	move.b	int_mode,d0
@@ -63,7 +61,7 @@ do_interrupt:
 	beq	int_do_mode1
 	cmpi.b	#1,d0
 	beq	int_do_mode0
-	jmp	(a0)
+	rts
 
 	;; This routine emulates a mode 0 interrupt.
 
diff --git a/main.asm b/main.asm
index 8ea0357..38b0e97 100644
--- a/main.asm
+++ b/main.asm
@@ -53,6 +53,8 @@ __main:
 
 	bsr	emu_setup
 	lea	emu_plain_op,a5
+
+	;; ... aaaaand we're off!
 	bsr	emu_run
 	bsr	emu_teardown
 
diff --git a/opcodes.asm.m4 b/opcodes.asm.m4
index 9a1598d..63ea0dc 100644
--- a/opcodes.asm.m4
+++ b/opcodes.asm.m4
@@ -100,7 +100,7 @@ _align	SET	0
 
 START	MACRO
 	ORG	emu_plain_op+_align
-_align	SET	_align+$40
+_align	SET	_align+$40	; opcode routine length
 	jmp	do_interrupt	; for interrupt routines
 	ENDM
 
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