Done with my first pass through the 1-byte opcodes.

4 files changed, 1220 insertions, 24 deletions

diff --git a/flags.asm b/flags.asm
index aa04118..928a6e7 100644
--- a/flags.asm
+++ b/flags.asm
@@ -84,6 +84,18 @@ FNPV_ok:
 	andi.b	#%00000100,d1
 	rts
 
+	;; Normalize and return Sign bit (loaded into Z bit).
+	;; Destroys d1
+f_norm_sign:
+	move.b	flag_valid-flag_storage(a3),d1
+	andi.b	#%01000000,d1
+	bne.s	FNsign_ok	; Bit is already valid
+	bsr	flags_normalize
+FNsign_ok:
+	move.b	flag_byte-flag_storage(a3),d1
+	andi.b	#%01000000,d1
+	rts
+
 	;; Routine to turn 68k flags into z80 flags.
 	;; Preconditions:
 	;;   Flags to change are noted in d0 by a 1 bit
diff --git a/interrupts.asm b/interrupts.asm
new file mode 100644
index 0000000..f76a0ff
--- /dev/null
+++ b/interrupts.asm
@@ -0,0 +1,4 @@
+ints_stop:
+	rts
+ints_start:
+	rts
diff --git a/main.asm b/main.asm
index 7a5d870..df9dc2c 100644
--- a/main.asm
+++ b/main.asm
@@ -46,15 +46,17 @@
 
 	;; Macro to read a byte from main memory at register \1.  Puts
 	;; the byte read in \2.
-FETCHB	MACRO			; 14 cycles, 4 bytes
-	;; XXX deref
-	move.b	0(a6,\1.w),\2
+FETCHB	MACRO
+	move.w	\1,d1
+	bsr	deref
+	move.b	(a0),\2
 	ENDM
 
 	;; Macro to write a byte in \1 to main memory at \2 (regs only)
-PUTB	MACRO			; 14 cycles, 4 bytes
-	;; XXX deref
-	move.b	\1,0(a6,\2)
+PUTB	MACRO
+	move.w	\2,d1
+	bsr	deref
+	move.b	\1,(a0)
 	ENDM
 
 	;; Macro to read a word from main memory at register \1
@@ -79,6 +81,7 @@ PUTW	MACRO			; 14 cycles, 4 bytes
 	ENDM
 
 	;; Push the word in \1 (register) using stack register a4.
+	;; Sadly, I can't trust the stack register to be aligned.
 	;; Destroys d0.
 
 	;;   (SP-2) <- \1_l
@@ -166,13 +169,6 @@ DONE	MACRO
 	;; == Special Opcode Macros ========================================
 
 
-	;; Do an ADD \1,\2
-F_ADD_W	MACRO
-	ENDM
-	;; Do an SUB \1,\2
-F_SUB_W	MACRO
-	ENDM
-
 	;; INC and DEC macros
 F_INC_B	MACRO
 	ENDM
@@ -206,6 +202,7 @@ _main:
 
 	include	"flags.asm"
 	include	"ports.asm"
+	include "interrupts.asm"
 
 emu_setup:
 	movea	emu_plain_op,a5
@@ -1868,7 +1865,8 @@ emu_op_c3:			; S12 T36
 emu_op_c4:
 	;; CALL	NZ,immed.w
 	;; If ~Z, CALL immed.w
-	;; XXX do this
+	bsr	f_norm_z
+	bne	emu_op_cd
 	DONE
 
 	START
@@ -1886,8 +1884,8 @@ emu_op_c6:
 
 	START
 emu_op_c7:
-	;; RST	immed.b
-	;;   CALL	0
+	;; RST	&0
+	;;  == CALL 0
 	;; XXX check
 	;; XXX FIX D2
 	move.l	d2,d1
@@ -1930,7 +1928,8 @@ emu_op_cb:			; prefix
 	START
 emu_op_cc:
 	;; CALL	Z,immed.w
-	;; XXX do this
+	bsr	f_norm_z
+	beq	emu_op_cd
 	DONE
 
 	START
@@ -1993,7 +1992,8 @@ emu_op_d3:
 	START
 emu_op_d4:
 	;; CALL	NC,immed.w
-	;; XXX do this
+	bsr	f_norm_c
+	beq	emu_op_cd
 	DONE
 
 	START
@@ -2049,7 +2049,8 @@ emu_op_db:
 	START
 emu_op_dc:
 	;; CALL	C,immed.w
-	;; XXX do this
+	bsr	f_norm_c
+	bne	emu_op_cd
 	DONE
 
 	START
@@ -2086,24 +2087,71 @@ emu_op_e1:
 
 	START
 emu_op_e2:
-	;; EX	(SP),HL
-	;; Exchange
+	;; JP	PO,immed.w
+	bsr	f_norm_pv
+	beq	emu_op_c3
+	DONE
+
 	START
 emu_op_e3:
+	;; EX	(SP),HL
+	;; Exchange
+	POPW	d1
+	PUSHW	d6
+	move.w	d1,d6
+	DONE
+
 	START
 emu_op_e4:
+	;; CALL	PO,immed.w
+	;; if parity odd (P=0), call
+	bsr	f_norm_pv
+	beq	emu_op_cd
+	DONE
+
 	START
 emu_op_e5:
+	;; PUSH	HL
+	PUSHW	d6
+	DONE
+
 	START
 emu_op_e6:
+	;; AND	immed.b
+	FETCHBI	d1
+	F_AND_B	d1,d3
+	DONE
+
 	START
 emu_op_e7:
+	;; RST	&20
+	;;  == CALL 20
+	;; XXX do this
+	DONE
+
 	START
 emu_op_e8:
+	;; RET	PE
+	;; If parity odd (P zero), return
+	bsr	f_norm_pv
+	bne	emu_op_c9
+	DONE
+
 	START
 emu_op_e9:
+	;; JP	(HL)
+	FETCHB	d6,d1
+	bsr	deref
+	movea	a0,a6
+	DONE
+
 	START
 emu_op_ea:
+	;; JP	PE,immed.w
+	bsr	f_norm_pv
+	bne	emu_op_c3
+	DONE
+
 	START
 emu_op_eb:
 	;; EX	DE,HL
@@ -2112,51 +2160,148 @@ emu_op_eb:
 
 	START
 emu_op_ec:
+	;; CALL	PE,immed.w
+	;; If parity even (P=1), call
+	bsr	f_norm_c
+	bne	emu_op_cd
+	DONE
+
 	START
 emu_op_ed:			; prefix
-
 	movea.w	emu_op_undo_ed(pc),a2
+	DONE
+
 	START
 emu_op_ee:
+	;; XOR	immed.b
+	FETCHBI	d1
+	F_XOR_B	d1,d3
+	DONE
+
 	START
 emu_op_ef:
+	;; RST	&28
+	;;  == CALL 28
+	;; XXX DO THIS
+	DONE
+
 	START
 emu_op_f0:
+	;; RET	P
+	;; Return if Positive
+	bsr	f_norm_sign
+	beq	emu_op_c9	; RET
+	DONE
+
 	START
 emu_op_f1:
+	;; POP	AF
+	;; SPEED this can be made faster ...
+	POPW	d3
+	move.w	d3,flag_byte-flag_storage(a3)
+	move.b	#$ff,flag_valid-flag_storage(a3)
+	DONE
+
 	START
 emu_op_f2:
+	;; JP	P,immed.w
+	bsr	f_norm_sign
+	beq	emu_op_c3	; JP
+	DONE
+
 	START
 emu_op_f3:
+	;; DI
+	bsr	ints_stop
+
 	START
 emu_op_f4:
+	;; CALL	P,&0000
+	;; Call if positive (S=0)
+	bsr	f_norm_sign
+	beq	emu_op_cd
+	DONE
+
 	START
 emu_op_f5:
+	;; PUSH	AF
+	bsr	flags_normalize
+	LOHI	d3
+	move.b	flag_byte-flag_storage(a3),d3
+	HILO	d3
+	PUSHW	d3
+	DONE
+
 	START
 emu_op_f6:
+	;; OR	immed.b
+	FETCHBI	d1
+	F_OR_B	d1,d3
+	DONE
+
 	START
 emu_op_f7:
+	;; RST	&30
+	;;  == CALL 30
+	;; XXX do this
+	DONE
+
 	START
 emu_op_f8:
+	;; RET	M
+	;; Return if Sign == 1, minus
+	bsr	f_norm_sign
+	bne	emu_op_c9	; RET
+	DONE
+
 	START
 emu_op_f9:
+	;; LD	SP,HL
+	;; SP <- HL
+	move.w	d6,d1
+	bsr	deref
+	movea	a0,a4
+	DONE
+
 	START
 emu_op_fa:
+	;; JP	M,immed.w
+	bsr	f_norm_sign
+	bne	emu_op_c3	; JP
+	DONE
+
 	START
-emu_op_fb:p
+emu_op_fb:
 	;; EI
+	bsr	ints_start
+	DONE
 
 	START
 emu_op_fc:
+	;; CALL	M,immed.w
+	;; Call if minus (S=1)
+	bsr	f_norm_sign
+	bne	emu_op_cd
+	DONE
+
 	START
 emu_op_fd:			; prefix
 	;; swap IY, HL
-
 	movea.w	emu_op_undo_fd(pc),a2
+
 	START
 emu_op_fe:
+	;; CP	immed.b
+	FETCHBI	d1
+	F_CP_B	d1,d3
+	DONE
+
 	START
 emu_op_ff:
+	;; RST	&38
+	;;  == CALL 38
+	;; XXX do this
+	DONE
 
 emu_op_undo_cb:
 
diff --git a/ports.asm b/ports.asm
index 4ca60f7..8244c3d 100644
--- a/ports.asm
+++ b/ports.asm
@@ -2,8 +2,1043 @@
 	;; bit that's unique to TI calculators.
 
 	;; Port is in d0, byte is in d1
+	;; Destroys a0
 port_in:
+	movea	lut_ports_in(pc,d0),a0
+	jmp	(a0)
 	rts
 
 port_out:
+	;; Fix this to work properly ...
+;	movea	lut_ports_in(pc,d0),a0
+	jmp	(a0)
 	rts
+
+lut_ports_in:
+	dc.l	port_in_00
+	dc.l	port_in_01
+	dc.l	port_in_02
+	dc.l	port_in_03
+	dc.l	port_in_04
+	dc.l	port_in_05
+	dc.l	port_in_06
+	dc.l	port_in_07
+	dc.l	port_in_08
+	dc.l	port_in_09
+	dc.l	port_in_0a
+	dc.l	port_in_0b
+	dc.l	port_in_0c
+	dc.l	port_in_0d
+	dc.l	port_in_0e
+	dc.l	port_in_0f
+	dc.l	port_in_10
+	dc.l	port_in_11
+	dc.l	port_in_12
+	dc.l	port_in_13
+	dc.l	port_in_14
+	dc.l	port_in_15
+	dc.l	port_in_16
+	dc.l	port_in_17
+	dc.l	port_in_18
+	dc.l	port_in_19
+	dc.l	port_in_1a
+	dc.l	port_in_1b
+	dc.l	port_in_1c
+	dc.l	port_in_1d
+	dc.l	port_in_1e
+	dc.l	port_in_1f
+	dc.l	port_in_20
+	dc.l	port_in_21
+	dc.l	port_in_22
+	dc.l	port_in_23
+	dc.l	port_in_24
+	dc.l	port_in_25
+	dc.l	port_in_26
+	dc.l	port_in_27
+	dc.l	port_in_28
+	dc.l	port_in_29
+	dc.l	port_in_2a
+	dc.l	port_in_2b
+	dc.l	port_in_2c
+	dc.l	port_in_2d
+	dc.l	port_in_2e
+	dc.l	port_in_2f
+	dc.l	port_in_30
+	dc.l	port_in_31
+	dc.l	port_in_32
+	dc.l	port_in_33
+	dc.l	port_in_34
+	dc.l	port_in_35
+	dc.l	port_in_36
+	dc.l	port_in_37
+	dc.l	port_in_38
+	dc.l	port_in_39
+	dc.l	port_in_3a
+	dc.l	port_in_3b
+	dc.l	port_in_3c
+	dc.l	port_in_3d
+	dc.l	port_in_3e
+	dc.l	port_in_3f
+	dc.l	port_in_40
+	dc.l	port_in_41
+	dc.l	port_in_42
+	dc.l	port_in_43
+	dc.l	port_in_44
+	dc.l	port_in_45
+	dc.l	port_in_46
+	dc.l	port_in_47
+	dc.l	port_in_48
+	dc.l	port_in_49
+	dc.l	port_in_4a
+	dc.l	port_in_4b
+	dc.l	port_in_4c
+	dc.l	port_in_4d
+	dc.l	port_in_4e
+	dc.l	port_in_4f
+	dc.l	port_in_50
+	dc.l	port_in_51
+	dc.l	port_in_52
+	dc.l	port_in_53
+	dc.l	port_in_54
+	dc.l	port_in_55
+	dc.l	port_in_56
+	dc.l	port_in_57
+	dc.l	port_in_58
+	dc.l	port_in_59
+	dc.l	port_in_5a
+	dc.l	port_in_5b
+	dc.l	port_in_5c
+	dc.l	port_in_5d
+	dc.l	port_in_5e
+	dc.l	port_in_5f
+	dc.l	port_in_60
+	dc.l	port_in_61
+	dc.l	port_in_62
+	dc.l	port_in_63
+	dc.l	port_in_64
+	dc.l	port_in_65
+	dc.l	port_in_66
+	dc.l	port_in_67
+	dc.l	port_in_68
+	dc.l	port_in_69
+	dc.l	port_in_6a
+	dc.l	port_in_6b
+	dc.l	port_in_6c
+	dc.l	port_in_6d
+	dc.l	port_in_6e
+	dc.l	port_in_6f
+	dc.l	port_in_70
+	dc.l	port_in_71
+	dc.l	port_in_72
+	dc.l	port_in_73
+	dc.l	port_in_74
+	dc.l	port_in_75
+	dc.l	port_in_76
+	dc.l	port_in_77
+	dc.l	port_in_78
+	dc.l	port_in_79
+	dc.l	port_in_7a
+	dc.l	port_in_7b
+	dc.l	port_in_7c
+	dc.l	port_in_7d
+	dc.l	port_in_7e
+	dc.l	port_in_7f
+	dc.l	port_in_80
+	dc.l	port_in_81
+	dc.l	port_in_82
+	dc.l	port_in_83
+	dc.l	port_in_84
+	dc.l	port_in_85
+	dc.l	port_in_86
+	dc.l	port_in_87
+	dc.l	port_in_88
+	dc.l	port_in_89
+	dc.l	port_in_8a
+	dc.l	port_in_8b
+	dc.l	port_in_8c
+	dc.l	port_in_8d
+	dc.l	port_in_8e
+	dc.l	port_in_8f
+	dc.l	port_in_90
+	dc.l	port_in_91
+	dc.l	port_in_92
+	dc.l	port_in_93
+	dc.l	port_in_94
+	dc.l	port_in_95
+	dc.l	port_in_96
+	dc.l	port_in_97
+	dc.l	port_in_98
+	dc.l	port_in_99
+	dc.l	port_in_9a
+	dc.l	port_in_9b
+	dc.l	port_in_9c
+	dc.l	port_in_9d
+	dc.l	port_in_9e
+	dc.l	port_in_9f
+	dc.l	port_in_a0
+	dc.l	port_in_a1
+	dc.l	port_in_a2
+	dc.l	port_in_a3
+	dc.l	port_in_a4
+	dc.l	port_in_a5
+	dc.l	port_in_a6
+	dc.l	port_in_a7
+	dc.l	port_in_a8
+	dc.l	port_in_a9
+	dc.l	port_in_aa
+	dc.l	port_in_ab
+	dc.l	port_in_ac
+	dc.l	port_in_ad
+	dc.l	port_in_ae
+	dc.l	port_in_af
+	dc.l	port_in_b0
+	dc.l	port_in_b1
+	dc.l	port_in_b2
+	dc.l	port_in_b3
+	dc.l	port_in_b4
+	dc.l	port_in_b5
+	dc.l	port_in_b6
+	dc.l	port_in_b7
+	dc.l	port_in_b8
+	dc.l	port_in_b9
+	dc.l	port_in_ba
+	dc.l	port_in_bb
+	dc.l	port_in_bc
+	dc.l	port_in_bd
+	dc.l	port_in_be
+	dc.l	port_in_bf
+	dc.l	port_in_c0
+	dc.l	port_in_c1
+	dc.l	port_in_c2
+	dc.l	port_in_c3
+	dc.l	port_in_c4
+	dc.l	port_in_c5
+	dc.l	port_in_c6
+	dc.l	port_in_c7
+	dc.l	port_in_c8
+	dc.l	port_in_c9
+	dc.l	port_in_ca
+	dc.l	port_in_cb
+	dc.l	port_in_cc
+	dc.l	port_in_cd
+	dc.l	port_in_ce
+	dc.l	port_in_cf
+	dc.l	port_in_d0
+	dc.l	port_in_d1
+	dc.l	port_in_d2
+	dc.l	port_in_d3
+	dc.l	port_in_d4
+	dc.l	port_in_d5
+	dc.l	port_in_d6
+	dc.l	port_in_d7
+	dc.l	port_in_d8
+	dc.l	port_in_d9
+	dc.l	port_in_da
+	dc.l	port_in_db
+	dc.l	port_in_dc
+	dc.l	port_in_dd
+	dc.l	port_in_de
+	dc.l	port_in_df
+	dc.l	port_in_e0
+	dc.l	port_in_e1
+	dc.l	port_in_e2
+	dc.l	port_in_e3
+	dc.l	port_in_e4
+	dc.l	port_in_e5
+	dc.l	port_in_e6
+	dc.l	port_in_e7
+	dc.l	port_in_e8
+	dc.l	port_in_e9
+	dc.l	port_in_ea
+	dc.l	port_in_eb
+	dc.l	port_in_ec
+	dc.l	port_in_ed
+	dc.l	port_in_ee
+	dc.l	port_in_ef
+	dc.l	port_in_f0
+	dc.l	port_in_f1
+	dc.l	port_in_f2
+	dc.l	port_in_f3
+	dc.l	port_in_f4
+	dc.l	port_in_f5
+	dc.l	port_in_f6
+	dc.l	port_in_f7
+	dc.l	port_in_f8
+	dc.l	port_in_f9
+	dc.l	port_in_fa
+	dc.l	port_in_fb
+	dc.l	port_in_fc
+	dc.l	port_in_fd
+	dc.l	port_in_fe
+	dc.l	port_in_ff
+
+lut_ports_out:
+	dc.l	port_out_00
+	dc.l	port_out_01
+	dc.l	port_out_02
+	dc.l	port_out_03
+	dc.l	port_out_04
+	dc.l	port_out_05
+	dc.l	port_out_06
+	dc.l	port_out_07
+	dc.l	port_out_08
+	dc.l	port_out_09
+	dc.l	port_out_0a
+	dc.l	port_out_0b
+	dc.l	port_out_0c
+	dc.l	port_out_0d
+	dc.l	port_out_0e
+	dc.l	port_out_0f
+	dc.l	port_out_10
+	dc.l	port_out_11
+	dc.l	port_out_12
+	dc.l	port_out_13
+	dc.l	port_out_14
+	dc.l	port_out_15
+	dc.l	port_out_16
+	dc.l	port_out_17
+	dc.l	port_out_18
+	dc.l	port_out_19
+	dc.l	port_out_1a
+	dc.l	port_out_1b
+	dc.l	port_out_1c
+	dc.l	port_out_1d
+	dc.l	port_out_1e
+	dc.l	port_out_1f
+	dc.l	port_out_20
+	dc.l	port_out_21
+	dc.l	port_out_22
+	dc.l	port_out_23
+	dc.l	port_out_24
+	dc.l	port_out_25
+	dc.l	port_out_26
+	dc.l	port_out_27
+	dc.l	port_out_28
+	dc.l	port_out_29
+	dc.l	port_out_2a
+	dc.l	port_out_2b
+	dc.l	port_out_2c
+	dc.l	port_out_2d
+	dc.l	port_out_2e
+	dc.l	port_out_2f
+	dc.l	port_out_30
+	dc.l	port_out_31
+	dc.l	port_out_32
+	dc.l	port_out_33
+	dc.l	port_out_34
+	dc.l	port_out_35
+	dc.l	port_out_36
+	dc.l	port_out_37
+	dc.l	port_out_38
+	dc.l	port_out_39
+	dc.l	port_out_3a
+	dc.l	port_out_3b
+	dc.l	port_out_3c
+	dc.l	port_out_3d
+	dc.l	port_out_3e
+	dc.l	port_out_3f
+	dc.l	port_out_40
+	dc.l	port_out_41
+	dc.l	port_out_42
+	dc.l	port_out_43
+	dc.l	port_out_44
+	dc.l	port_out_45
+	dc.l	port_out_46
+	dc.l	port_out_47
+	dc.l	port_out_48
+	dc.l	port_out_49
+	dc.l	port_out_4a
+	dc.l	port_out_4b
+	dc.l	port_out_4c
+	dc.l	port_out_4d
+	dc.l	port_out_4e
+	dc.l	port_out_4f
+	dc.l	port_out_50
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