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authorDuncan Smith2010-06-20 18:40:32 -0700
committerDuncan Smith2010-06-20 18:40:32 -0700
commit7f436d1dd95f575415070f35f05f29aa5c04cfd3 (patch)
treee35ffc853e1d6a00fbbec41e28df34b026115bb6 /main.asm
parent105b71eb2164c0dfb93bffc30f5e1cb0121f6e3a (diff)
Added WORD macro to rearrange bytes, ABCD -> ACBD
Diffstat (limited to 'main.asm')
-rw-r--r--main.asm26
1 files changed, 16 insertions, 10 deletions
diff --git a/main.asm b/main.asm
index 884ae19..d4e5f11 100644
--- a/main.asm
+++ b/main.asm
@@ -159,18 +159,24 @@ HILO MACRO ; 22 cycles, 2 bytes
rol.w #8,\1
ENDM
+ ;; Rearrange a register: ABCD -> ACBD.
+WORD MACRO
+ move.l \1,-(a7) ;12 cycles / 2 bytes
+ movep.w 0(a7),\1 ;16 cycles / 4 bytes
+ swap \1 ; 4 cycles / 2 bytes
+ movep.w 1(a7),\1 ;16 cycles / 4 bytes
+ addq #4,a7 ; 4 cycles / 2 bytes
+ ;; overhead: 52 cycles /14 bytes
+ ENDM
- ;; calc84maniac suggests putting emu_fetch into this in order
- ;; to save 8 cycles per instruction, at the expense of code
- ;; size
- ;;
- ;; See if I can get rid of the eor
+
+ ;; This is run at the end of every instruction routine.
DONE MACRO
- clr.w d0 ; 4 cycles
- move.b (a4)+,d0 ; 8 cycles
- rol.w #5,d0 ;16 cycles
- jmp 0(a5,d0.w) ;14 cycles
- ;; overhead: 42 cycles
+ clr.w d0 ; 4 cycles / 2 bytes
+ move.b (a4)+,d0 ; 8 cycles / 2 bytes
+ rol.w #5,d0 ;16 cycles / 2 bytes
+ jmp 0(a5,d0.w) ;14 cycles / 4 bytes
+ ;; overhead: 42 cycles /10 bytes
ENDM
;; == Special Opcode Macros ========================================