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authorAstrid Smith2011-10-31 00:26:51 -0700
committerAstrid Smith2011-10-31 00:26:51 -0700
commit58df7c903d62772c06ac5c8b1cc94d2f588953d1 (patch)
tree64d9b1db1157fd5f93ad5de1f4a62251f5f591f0 /opcodes.s.m4
parent555a832a8d8a26e81343ea059cbd39047134d864 (diff)
License clarification
Diffstat (limited to 'opcodes.s.m4')
-rw-r--r--opcodes.s.m429
1 files changed, 29 insertions, 0 deletions
diff --git a/opcodes.s.m4 b/opcodes.s.m4
index d4a9564..efd583a 100644
--- a/opcodes.s.m4
+++ b/opcodes.s.m4
@@ -98,6 +98,8 @@
|| To align opcode routines.
.set _align,0
+.ifndef TEST
+
.macro start
.org emu_plain_op+_align
.set _align,_align+0x100 | opcode routine length
@@ -128,6 +130,24 @@
.org emu_plain_op+_align+0x4A
.endm
+.else
+.macro START
+.endm
+.macro START_DD
+.endm
+.macro START_CB
+.endm
+.macro START_DDCB
+.endm
+.macro START_FD
+.endm
+.macro START_FDCB
+.endm
+.macro START_ED
+.endm
+
+.endif
+
|| LOHI/HILO are hideously slow for instructions used often.
|| Consider interleaving registers instead:
||
@@ -197,6 +217,7 @@
|| lookup table
+.ifndef TEST
|| This is run at the end of every instruction routine.
done:
clr.w d0 | 4 cycles / 2 bytes
@@ -215,6 +236,14 @@ done:
jmp 0(a5,d0.w) |14 cycles / 4 bytes
.endm
+.else
+done: rts
+
+.macro DONE
+ rts
+.endm
+.endif
+
|| Timing correction for more precise emulation
||
|| \1 is number of tstates the current instruction should take