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authorAstrid Smith2010-11-09 23:48:43 -0800
committerAstrid Smith2010-11-09 23:48:43 -0800
commit9ccaff138b0a3ae9b7f928768c3e766ee24ea654 (patch)
tree09450dc8e5e932714abf498fe3788246b99cd5b7 /opcodes_dd.asm
parent7fe1ea0f66c55bc57489feb6c3b0ba9ac22277c2 (diff)
Added guards around all routines that touch ePC or eSP.
These guards have one major fault I can see. I put them as early in the routine as possible, but it's still a distinct possibility that the 68k interrupt will fire between move.b (epc)+,d0 in macro DONE of one instruction and the call to HOLD_INTS in the following instruction. I don't have a good solution to this. I can use the hardware interrupt holding support to make everything a critical section except for the cycle gap before that instruction, but that makes _every_ instruction 24 cycles slower. I don't consider that an acceptable solution.
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